Difference between throughout and within of system verilog assertion

The SystemVerilog_3.1a LRM description:

The construct exp throughout seq is an abbreviation for:
(exp) [*0:$] intersect seq

The composite sequence, exp throughout seq, matches along a finite interval of consecutive clock ticks provided seq matches along the interval and exp evaluates to true at each clock tick of the interval. The following example is illustrated in Figure 17-11.
sequence burst_rule1;
@(posedge mclk)
$fell(burst_mode) ##0
(!burst_mode) throughout (##2 ((trdy==0)&&(irdy==0)) [*7]);
endsequence

The above should be modifiable as below:
(exp) [=1] intersect seq

which means that inside a sequence, the exp(or a signal) should at least once be true.

The construct seq1 within seq2 is an abbreviation for:
(1[*0:$] ##1 seq1 ##1 1[*0:$]) intersect seq2

The composite sequence seq1 within seq2 matches along a finite interval of consecutive clock ticks provided seq2 matches along the interval and seq1 matches along some sub-interval of consecutive clock ticks. That is, the matches of seq1 and seq2 must satisfy the following:
— The start point of the match of seq1 must be no earlier than the start point of the match of seq2.
— The end point of the match of seq1 must be no later than the end point of the match of seq2.

For example, the sequence
!trdy[*7] within (($fell irdy) ##1 !irdy[*8])
matches from clock tick 3 to clock tick 11 on the trace shown in Figure 17-12.

As per my analysis: 

The within is for sequence within the sequence. The throughout is for an expression within a sequence. The sequence being TRUE for [*0:$] time can be controlled by consecutive repetition (*), go to repetition (->) or non-consecutive repetition (=). For example, a signal has to be true at least for one clock cycle within a sequence(period of interval), we can use the throughout with go to repetition (->) operator. 

Adding worskspace switcher to the linux

Somehow in my linux vcn, the workspace switcher icon stopped showing up. For each poject, I had to open a new vnc session, else keep all files opened in the same workspace.

Finally got the solution:

In the linux home, write click on the lower most tab gives the below options. In the "Add to Panel" option, there is specific "Workspace Switcher" option. Just add it !!

Micro soft xls 2013 insert, cut, paste option grayed out !!!!

I have checked almost all the Google search links to find how to solve this. All were giving same solution of changing the option to have "Show Insert Option buttons". But even with this change my stupid xls was behaving same way.

Finally the below lines of the link http://www.askeygeek.com/reasonscauses-for-why-insert-button-is-greyed-out-on-the-developer-tab/ solved the problem.

A million thanks to Mahesh !!

How to find reason for randomize failure in questasim?

Many times our randomize() method call fails and the simulator ejects the failure message. But it is hard time finding the reason for the failure. Questasim has a switch for vsim, which will very clearly display the reason for the failure.   

vsim –solvefaildebug

UVM Verbosity management for ModelSim Questa

Generally the following code is used in the test case.

function void end_of_elaboration();
set_report_verbosity_level_hier(m_config.m_wb_wb_verbosity);
endfunction

The above is difficult option since for each change we need to put this and recompile. & simulate.

Easy method is +UVM_VERBOSITY=UVM_*
Where UVM_* can be UVM_FULL, UVM_DEBUG etc.

The funny thing is that the order of this command line argument is very important. It has to be put immediately after the test bench module name as below:
 vsim top_tb +UVM_VERBOSITY=UVM_*.

If we use them after other arguments, there is no effect !!! This is true only for Modelsim Questa.

Randomize uvm_driver

Many times we override the uvm_driver to generate error cases or to model delays to the driver. This happens in the build phase of the test case. The drawback here is that we need to have a separate test case for this. If it is an error test, then it makes sense to have a dedicated test case so that it can be regressed and debugged separately.

But when a delay model has to be implemented, it is better to have all kinds of delays in one random test. To cover all kinds of delays, I have used the following method.

Take the example of the driver which drives a message, which has header and couple of DWs of data. Now two kinds of delays are possible: inter-message-delay and inter-dw-delay. If we extend the driver to have separate constraints, we need separate tests for those.

But if we declare one more variable delay_model in the driver, we can randomize this in the test case itself. This saves number of tests.

driver.sv:

  rand int inter_dw_delay; 
  rand int inter_msg_delay;
  rand bit [1:0] delay_model; //
                              //00 - inter_dw_delay=0  & inter_msg_delay=0
                              //01 - inter_dw_delay=0  & inter_msg_delay=random 
                              //10 - inter_dw_delay=random  & inter_msg_delay=0 
                              //11 - inter_dw_delay=random  & inter_msg_delay=random
   

  constraint delay_order { 
    solve delay_model before inter_dw_delay;
    solve delay_model before inter_msg_delay;
  }
  constraint delay_c {
    if(delay_model==0) {
      inter_dw_delay ==0;
      inter_msg_delay ==0;
    }
    else if(delay_model==1) {
      inter_dw_delay ==0;
      inter_msg_delay dist {0:=30, [1:20]:=55, [21:100]:=10, [101:1000]:=5};
    }
    else if(delay_model==2) {
      inter_dw_delay dist {0:=60, [1:20]:=40};
      inter_msg_delay ==0;
    }
    else {
      inter_dw_delay dist {0:=60, [1:20]:=40};
      inter_msg_delay dist {0:=30, [1:20]:=55, [21:100]:=10, [101:1000]:=5};
    }
  }

In the above code, I have all the constraints in the driver. And in the test case, just randomize this driver, only for the delay_model. Other delays can be randomized in the driver run-time only. This covers all combinations of the delay in one single test case !

test.sv:

        if(!env.agnt.driver.randomize(delay_model))begin 
          `uvm_error(get_name(), $sformatf("env.agnt.driver.randomize failed"));
        end
        else begin
          `uvm_info(get_name(), $sformatf("driver.delay_model %2b", env.agnt.driver.delay_model), UVM_MEDIUM);
        end