How level triggered latch is converted to edge triggered flip-flop?

Question:

Difference between edge triggered and level triggered flip-flops?

Answer:

In level trigger mode, the input signal is sampled when the clock signal is either high or low whereas in edge trigger mode the input signal is sampled at rising or at the falling edge. Lever triggering is sensitive to glitches whereas edge trigger is non-sensitive. Example: latch for level trigger and flip-flop for edge trigger.

Main question:

How level triggered latch is converted to edge triggered flip-flop?

Answer:

It is using Master-Slave technique (Note that the D FF doesn't have any ambiguity when both inputs are same, because both inputs are never same for this. This problem is present only in SR FF).  The master is triggered in the positive edge while the slave is triggered in negative edge. But the negative edge at the slave is inverted version of the positive edge given to Master at the same time. It is not the next negative edge of the clock. So we never bother the pulse width!