How to get configuration object in top test bench

When we need to change a parameter/variable in the top test bench module for each test case, the following solution will be handy.

We had a top test bench module where a clock is generated. Because of limitations, we couldn't move that to the class environment. The clock delay for each test case was different and we had to control that from the test class. This value needs to be available at the top test bench module to be able to generate test-specific clock. We can achieve this by using uvm_config_db set/get way.

//---------------------------------------------------------------------------------------
// Config class where we declare the control_val
//---------------------------------------------------------------------------------------
class env_config extends uvm_object;
  .....
  .....
  reg [1:0] control_val;
endclass

//--------------------------------------------------------------------------------------
// Base test class where we get and initialize the control_val 
//--------------------------------------------------------------------------------------
class base_test extends uvm_test;
  .....
  .....
  env_config env_config_h;

  function build_phase (uvm_phase phase);
    super.build_phase();
    if(!uvm_config_db #(env_config)::get(this, "", "env_config", env_config_h)) 
    begin
      `uvm_error("Config Error" , "uvm_config_db #( env_config_h)::get cannot find resource data_port")
    end
    env_config_h.control_val = 2'b00; //default 
  endfunction
endclass

//-----------------------------------------------------------------------------------
//Specific test class where we change the control_val
//-----------------------------------------------------------------------------------
class spec_test extends base_test;
  ...
  ...
  function build_phase (uvm_phase phase);
    super.build_phase(); 
    env_config_h.control_val = 2'b11; //changed here  
  endfunction
endclass

//---------------------------------------------------------------------------------
// top test bench module, where config object & later clk is created
//---------------------------------------------------------------------------------
module top;
  .....
  .....
  reg clk = 0;
  realtime CLK_PERIOD;
  env_config env_config_h;
  initial begin
    env_config_h = new(); //can't do create
    uvm_config_db #( env_config )::set( null , "*" , "env_config" , env_config_h );
    #1; // this is very important that we wait until the class environment 
         // build assigns the new value at 0 time
    CLK_PERIOD = (env_config_h.control_val == 2'b10)? 100ps:(env_config_h.control_val == 2'b11)? 200ps:300ps;
    forever
      begin
        #(CLK_PERIOD / 2)
        clk = ~clk;
      end  
  end // initial
endmodule